Design Verification Engineer- ASIC, System Verilog UVM
Posted on: August 7, 2022
If you are a Design Verification Engineer- ASIC, System Verilog
UVM with experience, please read on!
What You Will Be Doing
((THIS POSITION REPORTS TO THE MILPITAS AREA OF CALIFORNIA AND
REQUIRES RELOCATION, PARTIAL REMOTE ALLOWED))
Primary Responsibilities Include
" Responsible for all aspects of verification methodology employed
and for ensuring the application of uniform standards and adoption
of best practices.
" Work and liaison with other Design Verification teams within our
customer sites to identify holes in the design verification flow
and implement corrective action.
" Overall, responsible for verification of ASIC designs To include
such things as:
- Design Verification Implement test benches in UVM and Sytem
Verilog, run regressions at RTL and gate level, generate and report
DV metrics with respect to bug tracking and code coverage, debug
failures and provide feedback to the design team.
- Responsible for oversight and completion of debugging problems
and troubleshooting in Real Time. This includes being responsible
for Debugging Designs for High throughput, Low Latency of Pipeline
and Dynamic Power Management at full system level.
- Setup Verification Regression suites at RTL Level &
Corresponding Netlist Level after Synthesis to test any/all Corner
" Work closely with design team to ensure the Company is meeting
design requirements for projects. This may include: review of
specifications, understanding chip architecture, developing tests &
coverage plans, and defining methodology & test benches.
" Work closely with Custom SoC department to provide great customer
service to our clients and the projects at hand. Support, encourage
and drive timely and accurate deliverables with customers within
" BS or MS in Computer Science or Electrical Engineering.
" 5-10+ years of industry experience bringing silicon ICs into high
" Must have strong experience with UVM.
" Must have a full chip verification experience
" Experience of leading a single project.
" Knowledge of industry standard interfaces. Extensive Familiarity
with Verilog, Simulation tools & demonstrated ability to debug
Problems & Troubleshoot in Real Time.
" Sound knowledge of ARMv8, interconnect, memory coherence and
" Familiarity with Formality & most popular Verification Tools.
(Key knowledge should include such topics as: IP validation, Gate
level verification, FPGA Validation, Emulation, Silicon Validation,
Reference Board bring up verification, Silicon Bring up, DFx, Low
" Expertise in writing Perl / Python , awk, sed & Common Scripts to
automate the Verification Tasks for CPU plus all Chip peripherals
USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers.
" Advanced knowledge of ASIC design and verification flow including
RTL design, simulation, test bench development, regression,
equivalence checking, timing analysis, scan insertion and test
" Experience with low-level programming of systems in C/C++.
" Experienced in writing scripts in languages such as Perl, Python,
" Functional understanding of constrained random verification
process, functional coverage, and code coverage.
" Low power verification UPF
" Team player with excellent communication skills and the desire to
take on diverse challenges.
" Customer interaction
" Good knowledge of low power camera and imaging systems is a
" Experience with formal verification tools is a plus.
" CPU Security, Secure boot, Secure JTAG
" Familiarity with ARM architecture
" Familiarity with scripting/programming with Perl/Python, Tcl,
What You Need for this Position
- Design Verification Engineer
- System Verilog UVM
- System Verilog
- Simulation Tools
- Dynamic Power Management
What's In It for You
- 100% paid benefits
- 7.5% match on 401(k)
- Generous PTO
So, if you are a Design Verification Engineer- ASIC, System Verilog
UVM with experience, please apply today!
Email Your Resume In Word To
Looking forward to receiving your resume through our website and
going over the position with you. Clicking apply is the best way to
apply, but you may also:
- Please do NOT change the email subject line in any way. You
must keep the JobID: linkedin : AG17-1698189L182 -- in the email
subject line for your application to be considered.***
Anya Glover - Executive Recruiter - CyberCoders
Applicants must be authorized to work in the U.S.
CyberCoders, Inc is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment
without regard to race, color, religion, sex, national origin,
disability, protected veteran status, or any other characteristic
protected by law.
Your Right to Work - In compliance with federal law, all persons
hired will be required to verify identity and eligibility to work
in the United States and to complete the required employment
eligibility verification document form upon hire.
Keywords: CyberCoders, Huntsville , Design Verification Engineer- ASIC, System Verilog UVM, Other , Huntsville, Alabama
Didn't find what you're looking for? Search again!